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Solutions for Advanced CMOS

The V93000 Smart Scale generation is designed to meet

the challenges of testing advanced, high-integration CMOS

technology.  Increased test coverage, faster time-to-market

and superior test economics are achieved with industry

leading digital performance, high-speed I/O flexibility,

system-like stress testing, protocol-engine-per-pin™

capabilities, real-time memory emulation, SmartLoop™

testing of symmetrical high-speed interfaces and enhanced

SmarTest™ software functionality.

Smarter Testing

ADVANTEST’s V93000 Smart Scale generation incorporates

innovative per-pin testing capabilities.

Each pin can

run with its own clock domain to match the exact data

rate requirements of the device under test, providing full

test coverage.  In addition, the testers are equipped for

power supply modulation, jitter injection and protocol

communication

Scalable platform combines the versatility to test

all types of semiconductor devices with “smart”

per-pin capabilities, enabling the industry’s most

cost-efficient test solutions

Reducing the cost of test requires not only innovative

technology, but also an extendable system architecture to

ensure long equipment lifetime for the greatest return on

customers’ capital investments.  ADVANTEST’s V93000

Smart Scale test platform is the semiconductor industry’s

first scalable, highly cost-efficient ATE solution to meet

these criteria, addressing the needs of leading IDMs,

foundries, design houses and OSATs around the world.

Scalable Tester Classes

Systems are available in four different classes – designated A,

C, S and L – featuring different test head sizes to provide the

most effective solution for each user’s specific applications.

These compatible tester classes allow users to quickly and

easily move their semiconductor devices from one Smart Scale

class to another as IC production volumes change over time.

T6373 Capable of 32 DUTs in Parallel Testing for 10-12 bit LCD Driver ICs

Global demand for LCD driver ICs is growing in response to an

expected sky rocketing in popularity for LCD televisions,

as well as liquid crystal panels for cellular phones with increasingly

rich feature sets. Tracking these developments, LCD driver ICs

are also growing in both pin count and function ality.

This evolution, however, has added to the importance of keeping

production costslow. The T6373 LCD driver test system offers an

optimal solution for customers facing this paradox.

Reducing Cost of Test for LCD Drivers with Large Pin Counts

The T6373 can be equipped with a maximum of 3.072 LCD channels

and 512 I/O channels. It supports four device parallel test for 640-pin

and 720-pin driver ICs, which will dominate in the future.

For driver ICs with BIST circuits, it could support up to 32 driver ICs.

Support for the Newest Driver ICs

The T6373’s high-speed/pre cision digitizer and DC (LCD ch) test

 unitare configured for per-pin operation. When testing many-pin/precision

(10 bit/1024 gradation) driver ICs, this tester boasts throughput of up 

to 150% greater than that of its predecessor.

Improved Support for Leveraging Legacy (T6372) Assets

By offering legacy support for the well-established test software, the

T6373 allows the customer to use valuable test assets, such as test

program environments, test boards, and probe cards,that supported

its predecessor model.

While preserving maximum compatibility with previous test systems,

the T6373 also allows the customer to minimize test costs.

Reducing cost of test by maximizing parallel test,allowing

flexible pin configurations

With greater test resourcesthan those of the T5377S, the T5383

supports greater device pin counts, and allows for higher levels of

parallelism:

up to 384 devices, 1.5 times greater than that of its prede cessor.

Also, its flexible pin assignment capability makes possible parallel

test with more flexibility and variety than ever before.

This granularity of tester resources optimizes test-cell configurations,

and further reduces cost of test.

Industry’s Fastest Test, Shortest Test Times

The T5383 operates at 286 MHz/572 Mbps, double the speed of T5377S,

making it the industry’s fastest offering in this product category.

This increased speed translates into shorter test times, as well as higher

fault coverage, including Known Good Die applications.

Further, enhanced memory repair analyzer hardware (the MRA4ev3

and DualAFMoption) delivers approximately double the throughput of

previous products. Faster processing speeds and dedicated high speed

data communications enable production bitmap yield learning. At the

same time, they prevent analysis times from increasing,even as device

counts and densities grow larger.

T5383

Parallel Test for Up to 384 Devices.

Flexible Pin Configuration Drives Lower Cost of Test.

In the DRAM manufacturing process, shrinking geometries

for 300 mm wafers are taking device densities and speeds to

a new level. At the same time, proliferating cellular tele

phones, personal computers,various digital appliances, are

propelling demand for memory, particularly multilayer SIP

(System-in-Package) devices. The T5383 provides a timely

response to these trends. From front-end test for DRAM to

back-end test for FLASH memory, MCP/SIP, and other devices,

the T5383 provides a high-throughput solution that offers flexible

support for increasingly fast and versatile memory devices.

In addition, T5383 high-density pin electronics deliver 50% more

capacity than provided by its prede cessor, T5377S, and within

the same small footprint.

Compatible with previous products

The T5383 uses FutureSuite, with its multi-language support, as its OS.

FutureSuite® is compatible with the ATL language, supporting thou

sands of applications, and also allows programming in ADVANTEST’s

C-based MCI (Multi Control Interface). These capabilities enable the

user to make selections tailored to evolving programming needs while

leveraging existing implementations.

Advantest’s T5503 8448

Channel Test Head addresses these needs, with superior throughput and lowered

test costs for high-speed manufacturing. When coupled with Advantest’s M6242

handler, the T5503 provides a DDR3 test cell that delivers performance and yield

as well as the industry’s lowest cost of volume production test.

Up to 3.2Gbps of test speed and 256 device parallel test For package test of the

new generation high-speed memory DDR3-SDRAM, the T5503 achieves the fastest

test speeds in the industry  of 3.2Gbps.

while delivering parallel test of up to 256 devices (four times that of its predecessors).

This contributes to a major reduction in test costs for high volume production lines and

makes it an ideal solution for DDR3-SDRAM, as well as for GDDR3 and GDDR4.

In addition, the T5503 provides an enriched multi-strobe function to measure the phase

difference between the reference clock signal and data output signals at each cycle,

— a significant benefit as the operating frequencies becomes higher.

This function helps to measure the characteristics of memory devices at high speeds

with a high level of accuracy.

Reduced power requirements and a space savings of 30% By adopting the latest CMOS

technology, a high degree of integration has been achieved in the semiconductor circuits

mounted on the tester. While realizing four times the parallel test capacity of the earlier

version, the new system configuration has a 30% smaller footprint, contributing to an

energy-efficient and space-saving production line environment.

Using FutureSuite®, with multi-language support Advantest’s proprietary FutureSuite

software with multi-language support enhances the system’s operating system.

In addition, the conventional ATL language, the MCI (Multi Control Interface)

language allows programming in C.

T5503

256-DUT Parallel Test Capacity for Mass Production Test of

High Speed DDR3-SDRAM Memory Devices

Broadband communications are now widely used in households and

businesses throughout the globe and expectations are growing for higher

quality and larger capacity applications including video, audio,and on-line content. 

The demand for low-power, very high-speed memory to drive these applications

is prompting the near-term transition from DDR2-SDRAM to DDR3-SDRAM.

DDR3’s increased performance, coupled with lower power requirements,

promise to measurably enhance the capabilities of equipment such as

PCs, notebooks and servers, as well as advanced consumer products

such as game consoles and HDTV.

Accompanying the shift from DDR2-SDRAM to the faster DDR3-SDRAM,

is a corresponding requirement from device manufacturers for higher-speed

and more accurate test capabilities, and an insistence on lowered test costs

for mass production of these new high-speed devices. Advantest’s T5503 8448

Channel Test Head addresses these needs, with superior throughput and lowered

test costs for high-speed manufacturing. 

Evolutionary Value Added Measurement System

In recent years the number of smart devices we use has increased significantly.

The role of the analog / sensor IC has become critically important not only in the

smart society but also in other fields. More than ever, higher performance,

tighter accuracy and longer reliability are required for those devices.

To address these challenges measurement systems need to have many features

while maintaining a very low test cost and engineers tasked with developing test

programs require very good coding skills plus in-depth operation knowledge of the

test system. The new highly integrated measurement system “EVA100” is supporting 

Power Supplies, SMU( 4 quadrant DC Signal Measurement Units ), Pattern Generators,

Arbitrary Waveform Generators, Digitizers and Oscilloscopes necessary for complete

analog / mixed-signal / sensor / digital IC devices and Modules including Electronic

Control Unit (ECU) for automotive evaluation and measurement.

This new measurement system allows engineers quickly to build their own

measurement environment without combining several standalone instruments.

The EVA100 Software GUI is extremely intuitive, requiring only drag & drop operation,

enabling engineers to create device focused measurement set ups in a very fast and

simple manner. Automatic report functions dramatically improve the efficiency of deskwork,

providing clear documentation and data ready for publishing in device data sheets.

Main Functions

Characteristics Evaluation

4 channels high frequency sampling digitizer to observe and measure transient

response waveforms or behavior of device under test(DUT).

Productivity Evaluation

The EVA100 automatically creates graphs of DUT characteristics and generates

HTML-format reports on measurement conditions and results, freeing users from

taking notes on each item to be evaluated. Files can be copied and downloaded in

CSV format, making it easier and quicker to create device evaluation reports

Functional Evaluation

The EVA100 automatically creates graphs of DUT characteristics and generates

HTML-format reports on measurement conditions and results, freeing users from

taking notes on each item to be evaluated. Files can be copied and downloaded in

CSV format, making it easier and quicker to create device evaluation reports

■ Documentation (Report Generator)

Sequence Editor makes it easy to synchronize multiple hardware channels based

on how the user determines when events occur. The Sequence Editor also supports

continuous measurement or conditional loop settings enabling greater control of

automated measurements. .

I2C, SPI, and JTAG I/F are supported by protocol based control. By preparing

the Register Map, we can use the register name for digital patterns instead of

mnemonics so that Register Map gives you a clear overview for the digital pattern

and improve the readability and efficiency of digital pattern debug.

Production Test

The EVA100 supports parallel measurement for production test. Users need only

set up connections to the desired number of DUTs to begin testing multiple

devices. The ability to use test sequences developed in the design phase also

reduces the number of processes required.

Product Features

The EVA100 is a new measurement system combining all necessary features

for device evalution, including support for analog voltage and current sources,

pattern generation, and waveform capture, in a single compact unit. Users

are liberated from the laborious work of setting up cables to connect multiple

measurement instruments. The EVA100 offers simultaneous control of all

functions with superior timing precision, achieving excellent reproducibility

of results without the need for ad hoc fixes.

Small

All necessary functions are integrated into the compact body (363mm x

472mm x 206mm) which has VI sources (AVI, MVI), General Control

Module(GCM) and Signal Capture(SCAP).

High Performance

The Event Master Sequencer (EMS) controls the hardware with high timing

accuracy and high precision enabling superior repeatability. Analog VI source,

General Control Module and Signal Capture instruments provide versatile

and comprehensive measurement capability.

Intuitive

“No programming language environment” offers very intuitive operation for

users, so that everyone from beginners to experts is able to use the system

quickly. Automatic report generation tools reduce the need for additional

deskwork, improving the efficiency of evaluation and measurement tasks

dramatically.

Expandable

Expandable architecture supports many scenarios from design to production

for analog and mixed signal devices. Supporting external instruments,

customized measurement systems can also be created according to more

specific requirements and needs.