NI PC-LPM-16/PnP Theory of Operation Multifunction I/O Board for the PC
The circuitry consists of Plug and Play address decoders, data buffers,
I/O channel interface timing control circuitry, and interrupt control
circuitry. The circuitry monitors address lines SA4 through SA15 to
generate the board enable signal, and uses lines SA0 through SA3 plus
timing signals to generate the onboard register select signals and
read/write signals. The data buffers control the direction of data transfer
on the bidirectional data lines based on whether the transfer is a read or
write operation.
The interrupt control circuitry routes any enabled interrupts to the
selected interrupt request line. The PC-LPM-16PnP has six interrupt
request lines available: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, and IRQ9.
The PC-LPM-16PnP generates interrupts in three different situations:
• When an A/D conversion generates data that can be read from FIFO
• When an active low-level signal is detected on the EXTINT* line
• When a rising-edge signal is detected on counter 2 output
The PC-LPM-16PnP individually enables and clears each one of these
interrupts. For more detailed information on generating interrupts
externally, see the EXTINTEN bit of the Command Register 1
description in Appendix D, Register-Level Programming.
Analog Input and Data Acquisition Circuitry
The PC-LPM-16PnP has 16 channels of analog input with 12-bit
A/D conversion. Using the timing circuitry, the PC-LPM-16PnP can
also automatically time multiple A/D conversions. Figure 3-3 shows a
block diagram of the analog input and data acquisition circuitry.