A High-Throughput Tester Optimal for Mass-production of

High-speed Devices such as DDR2-SDRAMs

As cell phones and notebook PCs become more compactand yet

incorporate ever more enhanced functionality, memory devices

have corre spondingly increased in speed and in storage capacity.

Meanwhile, volume-production solutions that deliver lower

overall cost-of-test for testing high-speed devices such as

DDR2-SDRAMs are in increased demand.

The T5588 meets such market demands with a maximum

testing rate of 800 Mbps and by allowing the simultaneous

testing of up to 512 devices. This enables high throughput

testing at greatly reducedcosts. T5588 is also the first DRAM

package tester to offer an optional flash memory test

function, making it uniquely adaptable to changing market

conditions.

Simultaneous Testing of Up to 512 Devices

The optimum number of pins for testing DDR2-SDRAMs

has been mounted on the T5588 to help it achieve simultaneous

testing of up to 512 devices.

Low Cost and Reduced Footprint

Owing to an original ASIC design developed using a cut ting-edge

CMOS process, the T5588 is able to cut costs by approximately 40%,

compared with our conventional model, and has a reduced footprint.

The Multi-language Operating System FutureSuite®

Use of the multi-language operating system FutureSuite allows

programming in the worldwide standard, C and ATL languages.