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ADVANTEST’s’ wide-range of optimally designed modules provides

flexible test solutions that can be tailored for all SoC device types.

Digital Consumer Test Solution

Expandability and Flexibility

Our 52-slot LS mainframe provides the lowest test cost for the

myriad of SoC devices and applications. Our modular architecture is

both flexible and expandable providing customers with the lowest

COT configuration for test requirement today and tomorrow.

Significant improvements in parallel test efficiency afford customers

a substantial test cost savings.

RF Test Solution

Independent quad-site RF resources (32 pin, VSG/VSA) achieve un

equalled levels of parallel test, and contribute significantly to a test

cost reduction for volume production.

Realize 70% test time reduction per DUT with multi-site efficiencies

greater than 85%

MCU Test Solution

Ideal coverage and broad functional ity for single-pass testing of MCU

devices with both embedded AD/DA, and Flash memory in a standard

T2000 configuration.

High-density channel resources and a newly developed pogo unit help

customers achieve massively parallel testing of MCU wafer probe devices.

Unique in its class, ADVANTEST’s new M4841 Dynamic Test Handler

enables high-throughput parallel test for very high volumes of devices

and supports complex ICs and pack ages, including BGA, CSP and QFP.

Because of its advanced performance capabilities and features, the

M4841 is the optimal dynamic test handler for high volume production

of devices used in consumer products such as portable digital equipment

and automotive systems.

■Reduced Cost of Test

The M4841 is capable of parallel test of up to 32 devices, four times

capability of the earlier, industry-leading handler, also from ADVANTEST .

The M4841 also delivers a high throughput of 18.500 devices per hour.

With three times the throughput capacity of its predecessor, the M4841

sets a new standard for the industry.  Because of its high test efficiency,

the M4841 is well suited for high-volume production lines.

With its unprecedented combination of 16-device parallel test and 18.500

device-per-hour throughput at 3 seconds test time or less, the M4841

makes a substantial contribution to reduced cost of test.

■Supports Test Across Wide Temperature Range

The M4841 maintains a constant temperature and devices can be

cooled to -40̊C or heated to 125̊C.  This wide temperature range ensures

that the M4841 can be used to simulate device application environments

with severe temperature ranges, such as those experienced in automo-

tive or avionics. By minimizing the effects of heating or cooling upon

throughput, the M4841 offers consistently high speeds and performance,

even at extreme temperatures.

■Modular Structure

The M4841 is designed so that users can choose the best configuration for

their needs; the number of devices for paralleltest, test temperature range

and throughput.  Because of the variety of configurations available for the M4841.

users can optimize the M4841 to not only meet their test needs but also

optimize cost, for a very efficient as well as very high performing handler solution.

M4841

High-Throughput Device Handler

for Volume Production Testing of MCUs and DSPs

Today’s semiconductors are gain ing in complexity both in circuit

design and packaging, and continue to be challenged by high

volume applications that function in environments with wide-rang

ing temperature fluctuations.

Semiconductor test and handling equipment must evolve to meet

these requirements, in the same way it must adapt to increasing

demands for higher parallelism and higher throughput.

Unique in its class, ADVANTEST’s new M4841 Dynamic Test Handler

enables high-throughput parallel test for very high volumes of devices

and supports complex ICs and pack ages, including BGA, CSP and QFP.

Because of its advanced performance capabilities and features, the

M4841 is the optimal dynamic test handler for high volume production

of devices used in consumer products such as portable digital equipment

and automotive systems.

A High Throughput Tester for Flexible Testing of Devices such as MCPs

As cell phones and notebook PCs become more compact and

yet incorporate ever more enhanced functionality, memory devices

have correspondingly increased in speed and in storage capacity.

Furthermore, the demand for stacked devices, such as DRAM + flash

devices and multi-chip packages (MCPs), has skyrocketed due to the

diversification of the end market usage. The T5587 is able to meet

this demand with its enhanced flash memory testing function and

high throughput, capable of a maximum testing rate of 400 Mbps

and simultaneously testing up to 512 devices.

Simultaneous Testing of Up to 512 Devices

The T5587 meets the higher throughput requirements of MCPs,

and achieves simulta neous testing of up to 512 devices.

Test Flash Memory Devices at High Speeds

The T5587 is capable of high-speed testing at 400 Mbps.

Furthermore, an enhanced bad block mask function and a newly

designed high-speed data transfer BUS enable this system to

drastically reduce the testing times for simulta neous testing of

NAND-type flash memory devices.

The Multi-language Operating System FutureSuite®

Use of the multi-language operating system FutureSuite allows

programming in the worldwide standard, C and ATL languages.

​The versatile T5833 memory test system combines industry

leading performance and low cost of test to maximize customers’

return on investment. The tester is designed to perform both wafer

sort and final test across a wide range of memory devices including

LPDDR3-DRAMs, MCPs, high-speed NAND flash memories and

next-generation non-volatile memory ICs.

High-Capacity Testing

The T5833 can achieve high throughput by simultaneously

performing wafer-level testing on 2.048 devices or final package

testing on 512 devices.

Known good die (KGD) testing can be conducted at speeds up to 2.4

Gbps.  In addition, the tester performs high-speed failure capture and

memory-redundancy analysis with AFM and MRA options, two key tasks

needed for memory wafer sort. These fast functions reduce test times

while enabling the recovery of more memory ICs for improved yields.

Designed for Scalability

The tester is built on ADVANTEST’s modular AS Platform, making

it configurable to meet each user’s specific needs.  The system is

scalable for applications ranging from device engineering to large

volume production, and its functionality can be extended with

module upgrades to handle future generations of devices.

The real-time source synchronous function increases yield and

reduces test times while the T5833’s tester-per-site architecture

reduces test times even further for NAND and other non-volatile

memory devices.

All-in-one system supports multifunctional testing of

DRAMs, NAND Flash devices, next-generation non

volatile memories and MCPs, the advanced memory

technologies at the heart of mobile electronics

To keep pace with users’ performance demands in the booming

market for mobile electronics, the semiconductors that drive smart

phones and tablet computers as well as the servers that support

them – primarily DRAMs, NAND Flash memories, multi-chip packages

(MCPs) and next-generation non-volatile memories including MRAM,

RRAM and PCM — are becoming faster and higher capacity.  This

raises the need for test solutions that have both the high functionality

to test today’s most advanced memory ICs and the cost-efficient

operation to address high-volume consumer markets.

The versatile T5833 memory test system combines industry

leading performance and low cost of test to maximize customers’

return on investment. The tester is designed to perform both wafer

sort and final test across a wide range of memory devices including

LPDDR3-DRAMs, MCPs, high-speed NAND flash memories and

next-generation non-volatile memory ICs.

High-speed test solution

ADVANTEST’s T5503HS system provides an optimal test

solution for double-data-rate SDRAMs and other next

generation memory chips. The tester can operate at speeds

up to 4.5 Gbps, fast enough to perform full-coverage testing

of the most advanced memories. In addition, the system

uses individual level settings, I/O dead-band canceling and

data-bus inversion (DBI) to maximize throughput in testing

high-speed devices.

To further enhance test performance, the T5503HS

automatically generates cyclic redundancy check (CRC) codes

and command/address (CA) parity codes to match the I/O

data rates and address of any DUT. This enables quick and

efficient development of new test programs, which reduces the

demands on customers’ resources while also improving the

time to market for new semiconductor designs.

Optimized for productivity

Capable of testing of up to 512 DDR4-SDRAM devices

in parallel, the T5503HS is a cost-effective, high-volume

test solution. The system’s real-time source-synchronous

function enables high throughput.  Additionally, an advanced

timing-training capability helps to identify the most effective

test solution faster than other systems on the global market.

Together, these functions allow the T5503HS tester to achieve

much higher productivity than software-based systems.

New tester delivers performance and speed

needed to test DDR4 and LPDDR4 memory ICs

used throughout portable electronics and servers

With today’s mobile electronic devices and the servers

that support them handling ever-increasing volumes

of data, semiconductor memory manufacturers need a

highly capable, cost-efficient means of testing their latest

generations of high-speed, high-capacity memory ICs –

including emerging DDR4-SDRAM and LPDDR4-SDRAM

chips. ADVANTEST’s T5503HS tester gives memory

manufacturers that industry-leading performance and a

low cost of test along with an upgradable system design.

Extendible lifetime

With its modular architecture, the T5503HS is designed to help

customers get the most value from their capital investments.

The system is available as a fully compatible upgrade on

ADVANTEST’s field-proven T5503 test platform.  This enables

users to extend the performance of their existing testers while

also getting greater ROI as next-generation ICs are introduced.

A High-Throughput Tester Optimal for Mass-production of

High-speed Devices such as DDR2-SDRAMs

As cell phones and notebook PCs become more compactand yet

incorporate ever more enhanced functionality, memory devices

have corre spondingly increased in speed and in storage capacity.

Meanwhile, volume-production solutions that deliver lower

overall cost-of-test for testing high-speed devices such as

DDR2-SDRAMs are in increased demand.

The T5588 meets such market demands with a maximum

testing rate of 800 Mbps and by allowing the simultaneous

testing of up to 512 devices. This enables high throughput

testing at greatly reducedcosts. T5588 is also the first DRAM

package tester to offer an optional flash memory test

function, making it uniquely adaptable to changing market

conditions.

Simultaneous Testing of Up to 512 Devices

The optimum number of pins for testing DDR2-SDRAMs

has been mounted on the T5588 to help it achieve simultaneous

testing of up to 512 devices.

Low Cost and Reduced Footprint

Owing to an original ASIC design developed using a cut ting-edge

CMOS process, the T5588 is able to cut costs by approximately 40%,

compared with our conventional model, and has a reduced footprint.

The Multi-language Operating System FutureSuite®

Use of the multi-language operating system FutureSuite allows

programming in the worldwide standard, C and ATL languages.

Application-specific Configurations

This versatile platform is available in various configurations,

each optimized to meet the customer’s distinct performance

and economic requirements:

•  The V93000 Versatile Digital solution addresses all

aspects of testing digital ICs, from wafer sorting to high-end

characterization.

•  For ICs for mobile applications, the V93000 Wireless/RF

solution can handle up to 96 ports with true octal-site and

high multi-site parallel efficiency at a minimal cost of test.

•  The V93000 SOC solution performs economic testing of

high-volume, cost-sensitive ICs while satisfying the testing

challenges of the latest mixed-signal devices used in

consumer electronics.

Scalable Tester Classes

Systems are available in four different classes – designated A,

C, S and L – featuring different test head sizes to provide the

most effective solution for each user’s specific applications.

These compatible tester classes allow users to quickly and

easily move their semiconductor devices from one Smart Scale

class to another as IC production volumes change over time.