Category: TEWS

Technical Information

 Form Factor: Standard single QMC conforming to

VITA 93.0

 Board size: 78.25 mm x 26 mm

 PCI Express 2.1 compliant interface

 Intel I210IT Gigabit Ethernet controller

 1000Base-T

 100Base-TX

 10Base-T

 IEEE 1588/802.1AS Precision Time Protocol (PTP)

 V1 and V2 PTP frame format

 IEEE 802.1Qav Audio/Video Bridging (AVB) traffic

shaper (with software extensions)

 16 Mbit serial flash storing configuration data and

providing memory for Boot ROM

 Operating temperature -40 °C to +85 °C

Application Information

The TQMC800 is a VITA 93.0 compatible single-width

QMC providing a one channel Ethernet 10Base-T /

100Base-TX / 1000Base-T interface.

The Intel I210IT Gigabit Ethernet Controller is accessible

via PCIe. The Ethernet interface supports 10. 100 and

1000 Mbit/s transmission rates and is equipped with a 16

Mbit Serial Flash to support PXE and iSCSI boot.

The Ethernet interface of the TQMC800 is capable of

performing an auto negotiation algorithm which allows

both link-partners to determine the best link-parameters.

The TQMC800 supports IEEE 1588/802.1AS Precision

Time Protocol (PTP) and IEEE 802.1Qav Audio/Video

Bridging (AVB) traffic shaping (with software extensions).

The Ethernet port of the TQMC800 is galvanically isolated

from the Ethernet controller and a LED on the board

indicates the network activity and link status.

The TQMC800 has an I²C board temperature sensor to

facilitate measurement of the board heat near the Ethernet

Controller.

The module meets the requirements to operate in

extended temperature range from -40°C to +85°C.

For operating systems not supported by Intel, please

contact TEWS.

The TQMC700 is available as air cooled and conduction

cooled variant.

Every TQMC701 is factory calibrated. The calibration

information is stored in a user-accessible on-board serial

EEPROM individual to every module. The correction data

values may be used to perform a hardware correction for

A/D channels per input range and D/A channels per output

range during functional operation.

In addition, there is a temperature sensor on every module

to allow supervisory and data temperature coherence

evaluation.

The TQMC701 provides different operation modes to

perform manual and automatic A/D and D/A conversions.

For automatic conversions there are dedicated A/D and

D/A sequencer units. These include on-board data buffer

and DMA controller for A/D data transfer, D/A data fetch

and conversion rate generators.

Sequencers provide optionally a Frame Mode for repetitive

frames of A/D and D/A conversions upon an internal or

external trigger signal event.

Conversion clock (conversion rate) and frame trigger

signals may be generated on-board for internal use.

Optionally these can be provided via the I/O connector if

the card is operating as a master card in a Multi-Board

configuration (externally synchronization). The conversion

clock (conversion rate) and frame trigger signals may also

be sourced externally to be used internally.

The TQMC701 is available as air cooled and conduction

cooled variant.

Application Information

The TQMC701 is a VITA 93.0 compatible single-width

QMC providing 8 channels of simultaneous sampling

single ended or true differential bipolar analog inputs, 4

channels of simultaneous update analog voltage output

and 16 ESD-protected 5 V tolerant TTL digital I/O lines.

The 16 bit analog input channels support per channel

software configurable input modes and voltage ranges.

Each channel can be operated in bipolar single-ended,

unipolar single-ended and bipolar differential mode. In the

single-ended modes it offers software selectable input

voltage ranges of 0-5 V, 0-10 V, 0-12.5 V, ±2.5 V, ±5 V,

±6.25 V, ±10 V and ±12.5 V. In differential mode the input

voltage ranges are selectable between ±5 V, ±10 V,

±12.5 V and ±20 V. Sampling rate for all channels active is

up to 1 Msps.

The 16 bit analog output channels support per channel

software configurable output voltage ranges of 0-5 V, 0

10 V, 0-10.8 V, ±5 V, ±10 V or ±10.8 V. The conversion

time is typ. 10 μs and the DAC outputs are capable to

drive a load of 2 kΩ, with a capacitance of up to 4000 pF.

All 16 digital I/O lines are ESD-protected and 5 V-tolerant.

Every I/O line is individually programmable as input or

output if not used for external synchronization. TTL I/O

lines can be set to high, low, or tristate.

Technical Information

 Form Factor: Standard single QMC conforming to

VITA 93.0

 Board size: 78.25 mm x 26 mm

 PCI Express 2.0 compliant interface

 Artix-7 User programmable FPGA

 Xilinx XC7A50T-2

 PCIe endpoint in FPGA

 128 Mbit SPI-EEPROM for FPGA configuration and

 User Data

 Digital I/O

 16 ESD-protected 5 V-tolerant TTL lines with

programmable pull- resistor

 Direction individually programmable

 8 channels 18 bit analog input

 Simultaneous sampling

 differential or single-ended inputs

 Programmable input voltage (one setting for all

channels):

Order Information

0-5 V, 0-10 V, 0-12.5 V,

±2.5 V, ±5 V, ±6.25 V, ±10 V, ±12.5 V

 Sampling rate: 1 Msps

 Overvoltage protection

 Factory calibration

 4 channels single-ended 16 bit analog output

 Simultaneous update

 Programmable output voltage:

0-5 V, 0-10 V, 0-10.8 V,

±5 V, ±10 V, ±10.8 V

 Conversion time: typ.10 μs

 Up to 2 kΩ resistive, 4000 pF capacitive load

 Overcurrent protection

 Factory calibration

 Operating temperature -40 °C to +85 °C

The User FPGA is configured by a SPI flash. An in-circuit

debugging option is available via the QMC’s JTAG

interface for read back and real-time debugging of the

FPGA design (using the Vivado ILA).

User applications for the TQMC700 with 7A50T FPGA can

be developed using the design software Vivado Design

Suite HL WebPACK Edition.

TEWS offers a well-documented basic FPGA Example

Application design. It includes a constraints file with all

necessary pin assignments and basic timing constraints.

The example design covers the main functionalities of the

TQMC700. It implements PCIe to register mapping and

basic I/O. It comes as a Xilinx Vivado Design Suite project

with source code and as a ready-to-download bit stream.

Application Information

The TQMC700 is a VITA93.0 compatible single-width

QMC offering a user programmable AMD Artix 7 7A50T

FPGA.

The TQMC700 provides 16 ESD-protected 5V-tolerant

TTL lines. All I/O lines are individually programmable as

input or output. TTL I/O lines can be set to high, low, or

tristate. Each TTL I/O line has a pull-resistor to a common

programmable pull-up voltage that can be set to +3.3 V,

+5 V and GND.

The 18 bit ADC offers 8 input channels, each of them has

a sampling rate of up to 1 Msps. Each channel can be

operated in bipolar single-ended, unipolar single-ended

and bipolar differential mode. In the single-ended modes it

offers software selectable input voltage ranges of 0-5 V, 0

10 V, 0-12.5 V, ±2.5 V, ±5 V, ±6.25 V, ±10 V and ±12.5V.

In differential mode the input voltages are selectable

between ±5 V, ±10 V, ±12.5 V and ±20 V. There is a

flexible digital filter offering a oversampling ratio up to 256.

The DAC offers 4 channels of 16 bit analog outputs with

software selectable output voltage ranges of 0-5 V, 0-10

V, 0-10.8 V, ±5 V, ±10 V or ±10.8 V. The output voltage

range can be individually set per channel. The conversion

time is typ. 10 μs and the DAC outputs are capable to

drive a load of 2 kΩ, with a capacitance up to 4000 pF.

Each TQMC700 is factory calibrated. The calibration

information is stored in an on-board serial EEPROM

unique to each TQMC700 module.

RoHS Compliant

TQMC600-10R-A 32 TTL I/O, Artix-7 7A50T FPGA, air cooled

TQMC600-10R-H 32 TTL I/O, Artix-7 7A50T FPGA, conduction cooled

TQMC600-11R-A 16 differential EIA-422 / EIA-485 I/O, Artix-7 7A50T FPGA, air cooled

TQMC600-11R-H 16 differential EIA-422 / EIA-485 I/O, Artix-7 7A50T FPGA, conduction cooled

TQMC600-12R-A 16 differential M-LVDS I/O, Artix-7 7A50T FPGA, air cooled

TQMC600-12R-H 16 differential M-LVDS I/O, Artix-7 7A50T FPGA, conduction cooled

For the availability of non-RoHS compliant (leaded solder) products please contact TEWS.

Software

TDRV020-SW-25 Integrity Software Support

TDRV020-SW-42 VxWorks Software Support

TDRV020-SW-65 Windows Software Support

TDRV020-SW-82 Linux Software Support

TDRV020-SW-95 QNX Software Support

For other operating systems please contact TEWS.

Related Products

TPCE210

2 Site QMC Carrier, PCIe x4. Gen2. low-profile, VHDCI-68 I/O

Technical Information

 Form Factor: Standard single QMC conforming to VITA 93.0

 Board size: 78.25 mm x 26 mm

 PCI Express 2.1 compliant interface

 Artix-7 User programmable FPGA

 Xilinx XC7A50T-2

 PCIe endpoint in FPGA

 128 Mbit SPI-EEPROM for FPGA configuration and User Data

 Digital I/O

 32 ESD-protected 5 V-tolerant TTL lines (-10R)

 16 differential EIA-422 / EIA-485 lines (-11R)

 16 differential M-LVDS lines (-12R)

 Direction individually programmable

 Operating temperature -40 °C to +85 °C

Order Information

 Digital I/O

 32 ESD-protected 5 V-tolerant TTL lines (-10R)

 16 differential EIA-422 / EIA-485 lines (-11R)

 16 differential M-LVDS lines (-12R)

 Direction individually programmable

 Operating temperature -40 °C to +85 °C

Application Information

The TQMC600 is a VITA 93.0 compatible single-width

QMC offering a user programmable AMD Artix 7 7A50T

FPGA.

Depending on the order option the TQMC600 offers 32

ESD-protected 5V-tolerant TTL lines or 16 differential I/O

lines using ESD-protected EIA-422 / EIA-485 compatible

line transceivers or Multipoint-LVDS transceivers.

All I/O lines are individually programmable as input or

output. TTL I/O lines can be set to high, low, or tristate.

Differential I/O lines are terminated, EIA-422 / EIA-485

lines with 120 Ω, M-LVDS lines with 100 Ω.

The User FPGA is configured by a SPI flash. An in-circuit

debugging option is available via the QMC’s JTAG

interface for read back and real-time debugging of the

FPGA design (using the Vivado ILA).

User applications for the TQMC600 with 7A50T FPGA can

be developed using the design software Vivado Design

Suite HL WebPACK Edition.

TEWS offers a well-documented basic FPGA Example

Application design. It includes a constraints file with all

necessary pin assignments and basic timing constraints.

The example design covers the main functionalities of the

TQMC600. It implements PCIe to register mapping and

basic I/O. It comes as a Xilinx Vivado Design Suite project

with source code and as a ready-to-download bit stream.

The TQMC600 is available as air cooled and conduction

cooled variant.