Multibus II

From Idea to Standard

In the early 1980s some manufacturers build a consortium together with Intel in order to

improve and standardize a bus architecture “Multibus II” which is based on Multibus I.

The new system should offer the following key features:

• Eurocard board sizes and DIN-connectors

• self-test capability

• software jumpers for configuration

• fast 32-bit bus

• functional partitioning (using LAN concepts)

• reliability

• inter-operability

These properties were defined 1987 in the standard IEEE 1296 as Multibus II-standard.

Definition

The standard IEEE 1296 describes the function of Multibus II as follows (abstract):

MULTIBUS II is parallel system bus (PSB). It provides a high-performance backplane bus

intended for use in multiple processor systems, with synchronous, 32-bit multiplexed ad

dress/data, with error detection, using a 10 MHz bus clock. The bus performance is

approx. 32 to 40 MByte/s. Current systems offer up to 80 MByte/s.