The User FPGA is configured by a SPI flash. An in-circuit

debugging option is available via the QMC’s JTAG

interface for read back and real-time debugging of the

FPGA design (using the Vivado ILA).

User applications for the TQMC700 with 7A50T FPGA can

be developed using the design software Vivado Design

Suite HL WebPACK Edition.

TEWS offers a well-documented basic FPGA Example

Application design. It includes a constraints file with all

necessary pin assignments and basic timing constraints.

The example design covers the main functionalities of the

TQMC700. It implements PCIe to register mapping and

basic I/O. It comes as a Xilinx Vivado Design Suite project

with source code and as a ready-to-download bit stream.

Application Information

The TQMC700 is a VITA93.0 compatible single-width

QMC offering a user programmable AMD Artix 7 7A50T

FPGA.

The TQMC700 provides 16 ESD-protected 5V-tolerant

TTL lines. All I/O lines are individually programmable as

input or output. TTL I/O lines can be set to high, low, or

tristate. Each TTL I/O line has a pull-resistor to a common

programmable pull-up voltage that can be set to +3.3 V,

+5 V and GND.

The 18 bit ADC offers 8 input channels, each of them has

a sampling rate of up to 1 Msps. Each channel can be

operated in bipolar single-ended, unipolar single-ended

and bipolar differential mode. In the single-ended modes it

offers software selectable input voltage ranges of 0-5 V, 0

10 V, 0-12.5 V, ±2.5 V, ±5 V, ±6.25 V, ±10 V and ±12.5V.

In differential mode the input voltages are selectable

between ±5 V, ±10 V, ±12.5 V and ±20 V. There is a

flexible digital filter offering a oversampling ratio up to 256.

The DAC offers 4 channels of 16 bit analog outputs with

software selectable output voltage ranges of 0-5 V, 0-10

V, 0-10.8 V, ±5 V, ±10 V or ±10.8 V. The output voltage

range can be individually set per channel. The conversion

time is typ. 10 μs and the DAC outputs are capable to

drive a load of 2 kΩ, with a capacitance up to 4000 pF.

Each TQMC700 is factory calibrated. The calibration

information is stored in an on-board serial EEPROM

unique to each TQMC700 module.

RoHS Compliant

TQMC600-10R-A 32 TTL I/O, Artix-7 7A50T FPGA, air cooled

TQMC600-10R-H 32 TTL I/O, Artix-7 7A50T FPGA, conduction cooled

TQMC600-11R-A 16 differential EIA-422 / EIA-485 I/O, Artix-7 7A50T FPGA, air cooled

TQMC600-11R-H 16 differential EIA-422 / EIA-485 I/O, Artix-7 7A50T FPGA, conduction cooled

TQMC600-12R-A 16 differential M-LVDS I/O, Artix-7 7A50T FPGA, air cooled

TQMC600-12R-H 16 differential M-LVDS I/O, Artix-7 7A50T FPGA, conduction cooled

For the availability of non-RoHS compliant (leaded solder) products please contact TEWS.

Software

TDRV020-SW-25 Integrity Software Support

TDRV020-SW-42 VxWorks Software Support

TDRV020-SW-65 Windows Software Support

TDRV020-SW-82 Linux Software Support

TDRV020-SW-95 QNX Software Support

For other operating systems please contact TEWS.

Related Products

TPCE210

2 Site QMC Carrier, PCIe x4. Gen2. low-profile, VHDCI-68 I/O

Technical Information

 Form Factor: Standard single QMC conforming to VITA 93.0

 Board size: 78.25 mm x 26 mm

 PCI Express 2.1 compliant interface

 Artix-7 User programmable FPGA

 Xilinx XC7A50T-2

 PCIe endpoint in FPGA

 128 Mbit SPI-EEPROM for FPGA configuration and User Data

 Digital I/O

 32 ESD-protected 5 V-tolerant TTL lines (-10R)

 16 differential EIA-422 / EIA-485 lines (-11R)

 16 differential M-LVDS lines (-12R)

 Direction individually programmable

 Operating temperature -40 °C to +85 °C

Order Information

 Digital I/O

 32 ESD-protected 5 V-tolerant TTL lines (-10R)

 16 differential EIA-422 / EIA-485 lines (-11R)

 16 differential M-LVDS lines (-12R)

 Direction individually programmable

 Operating temperature -40 °C to +85 °C

Application Information

The TQMC600 is a VITA 93.0 compatible single-width

QMC offering a user programmable AMD Artix 7 7A50T

FPGA.

Depending on the order option the TQMC600 offers 32

ESD-protected 5V-tolerant TTL lines or 16 differential I/O

lines using ESD-protected EIA-422 / EIA-485 compatible

line transceivers or Multipoint-LVDS transceivers.

All I/O lines are individually programmable as input or

output. TTL I/O lines can be set to high, low, or tristate.

Differential I/O lines are terminated, EIA-422 / EIA-485

lines with 120 Ω, M-LVDS lines with 100 Ω.

The User FPGA is configured by a SPI flash. An in-circuit

debugging option is available via the QMC’s JTAG

interface for read back and real-time debugging of the

FPGA design (using the Vivado ILA).

User applications for the TQMC600 with 7A50T FPGA can

be developed using the design software Vivado Design

Suite HL WebPACK Edition.

TEWS offers a well-documented basic FPGA Example

Application design. It includes a constraints file with all

necessary pin assignments and basic timing constraints.

The example design covers the main functionalities of the

TQMC600. It implements PCIe to register mapping and

basic I/O. It comes as a Xilinx Vivado Design Suite project

with source code and as a ready-to-download bit stream.

The TQMC600 is available as air cooled and conduction

cooled variant.

Technical Information

 Form Factor: Standard single QMC conforming to

VITA 93.0

 Board size: 78.25 mm x 26 mm

 PCI Express 2.1 compliant interface

 FPGA based PCIe endpoint

 Four high speed synchronous / asynchronous serial

interface channels

 Support of differential RXD, RXCLK, TXD, TXCLK per

channel

 ESD protected I/O lines for EIA-422. EIA-485 FD

(Full-Duplex)

 Maximum Data Rate: 10 Mbit/s Synchronous, 2 Mbit/s

Asynchronous

 Operating temperature -40 °C to +85 °C

Order Information

 ESD protected I/O lines for EIA-422. EIA-485 FD

(Full-Duplex)

 Maximum Data Rate: 10 Mbit/s Synchronous, 2 Mbit/s

Asynchronous

 Operating temperature -40 °C to +85 °C

RoHS Compliant

TQMC401-10R-A Four Channel High Speed Sync/Async Serial Interface, air cooled

TQMC401-10R-H Four Channel High Speed Sync/Async Serial Interface, conduction cooled

For the availability of non-RoHS compliant (leaded solder) products please contact TEWS.

Software

TDRV009-SW-25 Integrity Software Support

TDRV009-SW-42 VxWorks Software Support

TDRV009-SW-65 Windows Software Support

TDRV009-SW-82 Linux Software Support

TDRV009-SW-95 QNX Software Support

For other operating systems please contact TEWS.

Related Products

TPCE210

2 Site QMC Carrier, PCIe x4. Gen2. low-profile, VHDCI-68 I/O

Application Information

The TQMC401 is a VITA 93.0 compatible single-width

QMC providing four high speed serial data communication

channels.

The serial communication controller is implemented in

FPGA logic along with the bus master capable PCIe

interface, guaranteeing long term availability and having

the option to implement additional functions in the future.

Data transfer to and from host memory is handled via

TQMC401 initiated DMA cycles for minimum host/CPU

intervention.

Each channel has a receive and transmit FIFO of 512 long

words (32 bit) per channel for high data throughput.

Several serial communication protocols are supported for

each channel, such as asynchronous (with oversampling),

isochronous, synchronous and HDLC mode.

Available signal encodings for synchronous data

communication are NRZ, NRZI, FM0. FM1 and

Manchester.

Available clock sources are 14.7456 MHz for standard

asynchronous baud rates, 10 MHz for the 10 Mbit/s

synchronous data rate and 24 MHz for other baud or data

rates.

Each channel provides various interrupt sources which

can be enabled or disabled individually.

The Differential I/O lines for EIA-422. EIA-485 Full-Duplex

are terminated with 120 Ω on-board.

The TQMC401 is available as air cooled and conduction

cooled variant.

Technical Information

 Form Factor: Standard single QMC module

conforming to VITA 93.0

 Board size: 26 mm x 78.25 mm

 PCI Express 2.0 Gen1 (2.5Gbps) compliant interface

 IPMI resource: FRU hardware definition information

stored in on-board EEPROM 

 Asynchronous serial interface

 Quad UART: Exar XR17V354

 Programmable Interfaces:

 RS232

 RS422

 RS485 full-duplex

 RS485 half-duplex

 On-chip switchable 120Ω Termination for each

RS422/RS485 channel

 Support of full modem RS232 (RxD, TxD, RTS, CTS,

DTR, DSR, CD, RI and GND)

  RxD+/-, TxD+/- and GND for each RS422/RS485 FD

channel; D+/- and GND for each RS485 HD channel

 Programmable data rates:

 RS232: up to 1 Mbps

 RS422/RS485: up to 20 Mbps

 256 byte transmit and receive FIFO per channel

 Readable FIFO levels

 Global Interrupt Source Register

 General Purpose 16 bit Timer/Counter

 Operating temperature -40 °C to +85 °C

 MTBF (MIL-HDBK217F/FN2 GB 20 °C)

 TQMC400-10R: 1530000 h

Application Information

The TQMC400 is a VITA 93.0 compatible Small Form

Factor Mezzanine Card (QMC) offering 4 UART channels

with multiprotocol transceivers. Each channel can be

programmed to operate as an RS232. RS422/RS485 full

duplex or RS485 half-duplex interface.

Each RS232 channel supports RxD, TxD, RTS, CTS,

DTR, DSR, CD, RI and GND. RS422 and RS485 full

duplex supports a four wire interface (RX+, RX-, TX+, TX-)

plus ground (GND). RS485 half-duplex supports a two

wire interface (DX+, DX-) plus ground (GND). On-chip

switchable termination of 120Ω is provided for the

RS422/RS485 interfaces.

Selectable data rates are up to 1 Mbps for RS232 mode

and 20 Mbps for RS422/RS485 half-duplex and full-duplex

mode. Additionally a reduced slew rate mode with lower

EMI provides data rates with max. 250 kbps for RS232

and max. 500 kbps for RS422/RS485.

Each channel has 256 byte transmit and receive FIFOs to

significantly reduce the overhead required to provide data

to and get data from the transmitters and receivers. The

FIFO trigger levels are programmable. The UART offers

readable FIFO levels.

Software Support (TDRV002-SW-xx) for different

operating systems is available.

The TQMC400 is available as air cooled and conduction

cooled variant.

Technical Information

 Form Factor: PCI Express x4 Revision 2.0

 Board size: low-profile, half-length

(167.65 x 68.9 mm)

 PCIe Speed: max. 5GT/s (dependent on the

mounted QMC modules)

 Two single QMC sites:

 PCIe Interface x4. Rev. 2.0

 Front-panel I/O access via VHDCI-68

 Unique header with JTAG Signals routed to each

QMC connector

 Management Controller

 QMC FRU EEPROM and sensor access

 Surveillance of QMC health status

 Operating temperature -40 °C to +85 °C

 MTBF (MIL-HDBK217F/FN2 GB 20 °C)

 TPCE210-10R: 959000h