Hardware Tips and Specifications

The DS200FCGDH1B is a door assignment and status card (FCGD). Developed by General Electric for its Mark V board family, the card can be installed in many GE-branded drives.

Once installed, the card acts as the interface system for a six-pulse phase control non-inverting bridge. the DSPC (Digital Signal Processing Card) relays information to the board for decryption.

This generates signals about diagnostic information and system feedback. This generates signals for diagnostic information and system feedback, which are then sent out using the drive’s integrated VME backplane.

This DS200FCGDH1B product collects a large amount of data from the drive’s integrated DSPC. The signals received by the board are converted to unit gating signals.

All system bridge pins receive this cell gating signal and return multiplexed cell status information to the card. the FCGD board also receives and scales feedback signals.

The three FGPA boards send feedback signals through fiber optic connections on the board. The included feedback includes frequency, voltage, and board status information.

The integrated IMOK LED status indicator provides the user with basic system status.

Board installation parameters provided by the manufacturer should be met to minimize the risk of equipment failure or error. Board functionality is dependent on proper wiring of the system.

An illustrated guide for wiring and installing the DS200FCGDH1B is provided in the equipment manual and data sheet. The entire Mark V series was originally powered by General Electric.

The above additional information for this DS200FCGDH1B printed circuit board product is largely reminiscent of the general Mark V Series instruction documentation and visual inspection of the DS200FCGDH1B unit itself.

This strategy was deemed necessary due to the legacy series status of this DS200FCGDH1B product and the concomitant lack of on-line instructional manual material that could be utilized for research purposes on this page.

With this in mind, the DS200FCGDH1B functional product number itself can be considered an important source of information on DS200FCGDH1B Board hardware components and component specifications.

About the DS200ITXDG1ABA

The DS200ITXDG1ABA board is labeled as a Dynamic Brake Buffer Board and is part of the Mark V Series manufactured by General Electric.

The Mark V Series, of which this DS200ITXDG1ABA product is a part, was one of the last of General Electric’s Mark product line to incorporate Speedtronic control system technology into its various products.

And since it was eventually discontinued many years after its initial release, it exists as a legacy product line.

This DS200ITXDG1ABA Printed Circuit Board, or PCB for short, is not an original development for its specific Mark V Turbine Control System family of functional roles; it is actually the DS200ITXDG1 Parent Dynamic Brake Buffer Board.

The DS200ITXDG1ABA PCB is conspicuously missing all three versions of the three important product versions of the DS200ITXDG1ABA PCB.

The assembly of this DS200ITXDG1ABA PCB has been specifically altered to utilize a Level A Major Function Revision, a Level B Minor Function Revision, and a Level A Drawing Configuration Revision.

Hardware Tips and Specifications

The required operation of the IXTD board is provided through the circuitry of the connected power supply/interface board (IMCP). When the IMCP and the IXTD board are connected, they are connected via a four-pin connector.

When the board is installed, it will be externally mounted and must be sized to meet the worst-case switching requirements of dynamically braked IGBTs.

The purpose of the snubber board is to be used to limit voltage transients at both ends of the IGBT and at all known operating conditions of the driver.

Another function of the DS200ITXDG1ABA board is to regulate the output of the IGBT gate driver board to match the electrical characteristics of the AT frame driver.

AT frame drivers are available in variable and constant torque applications. The drive output current rating for variable torque applications is 500 ARMS.

The DS200ITXDG1ABA board has three connector types: bus I/O connectors, input connectors for DBPL, and board pin connectors.

All of these connector types have different pin numbers, nomenclature, and descriptions, which are explained in depth and in detail in the DS200ITXDG1ABA instruction manual included above for your convenience.

Features

– High-speed, easy-to-use fiber optic network (170 Mbaud serial rate)

– Data written to the memory of one node is also written to the memory of all nodes on the network

– Up to 2.000 meters between nodes, up to 256 nodes can be connected

– Data transfer rate of 6.2 Mbyte/s without redundancy

– Data transfer rate of 6.2 Mbyte/s without redundancy Data transfer rate of 3.2 Mbyte/s with redundancy

– Any node on the network can generate an outage in any other node on the network or in all network nodes with a single command

– Error detection – redundant transmission mode suppresses errors

– No processor overhead

– Processor is not involved in network operation

– Up to 1 Mbyte of reflected memory

– A24:A32:D32:D16:D8 Memory Access

– Single 6U VMEbus board

Product Overview

-The Reflective Memory concept provides a very fast and efficient way to share data between distributed computer systems.

VMIC’s VMIVME-5576 Reflective Memory interface allows data to be shared between up to 256 independent systems (nodes) at rates of up to 6.2 Mbyte/s. Each Reflective Memory board can be configured with up to 256 nodes.

Each Reflective Memory board can be configured with 256 Kbytes to 1 Mbyte of on-board SRAM. local SRAM allows fast reads of stored data.

Write data is stored in the local SRAM and broadcast to other Reflective Memory nodes via a high-speed fiber optic data path.

Data transfers between nodes are software transparent, so there is no I/O overhead.

Transmit and receive FIFOs buffer data during peak data rates to optimize CPU and bus performance and maintain high data throughput.

Reflective memory also allows interrupts to one or more nodes by writing to byte registers.

These interrupt (tertiary, user-definable) signals can be used to synchronize system processes or to follow any previous data.

Interrupts always follow the data to ensure that the data is received before the interrupt is acknowledged.